发明名称 Test circuit for semiconductor integrated logic circuit using tristate buffers allowing control circuit for tristate to be tested
摘要 In a semiconductor integrated logic circuit including a tri-state output buffer having three different output conditions of a logical high level, a logical low level and a high impedance condition, and an internal control circuit generating a control signal for controlling the tri-state output buffer, a first selector is provided which has a first input receiving a data signal outputted from an internal logic circuit, a second input connected to receive the control signal, and an output connected to an data input of the tri-state output buffer. A second selector is provided which has a first input connected to receive the control signal, and a second input connected to a logic high level which brings the tri-state buffer into an output enable condition in which the tri-state output buffer outputs either the logical high level or the logic low level. An output of the second selector is connected to a control input of the tri-state output buffer. A common switch signal is supplied in common to an selection control input of each of the first and second selectors. When the common switch signal is indicative of a test mode, the first selector selects and outputs the control signal to the data input of the tri-state output buffer and the second selector selects and outputs the logic high level to the control input of the tri-state output buffer so that the tri-state buffer is brought in the output enable condition so as to output the control signal.
申请公布号 US6028443(A) 申请公布日期 2000.02.22
申请号 US19970948919 申请日期 1997.10.10
申请人 NEC CORPORATION 发明人 OZAKI, HIDEHARU
分类号 G01R31/28;G01R31/3185;H01L21/822;H01L27/04;(IPC1-7):H03K19/00 主分类号 G01R31/28
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