| 摘要 |
A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.
|
