发明名称 coupled noise estimation method for on-chip interconnects
摘要 An efficient method for identifying potential noise failures in an integrated circuit design by predicting peak noise within a victim circuit of an integrated circuit. Initially, a victim circuit within an integrated circuit is located. An aggressor circuit within the integrated circuit is located which has a physical relationship with the victim circuit, normally proximity. The slope of a signal within the aggressor circuit is analyzed and the coupling currents induced in the victim circuit by the aggressor circuit are computed. The input slope of the aggressor circuit and the physical relationship between the victim circuit and the aggressor circuit are utilized to determine a peak current induced into the victim circuit utilizing modelled coupling capacitance. The peak current and the equivalent impedance of the victim circuit can be utilized to determine peak noise. Noise failures on integrated circuits can be avoided by detecting peak noise which is above acceptable levels.
申请公布号 US6029117(A) 申请公布日期 2000.02.22
申请号 US19970963278 申请日期 1997.11.03
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 DEVGAN, ANIRUDH
分类号 G01R31/00;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/00
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