发明名称 MULTIPLEX CONVERSION DEVICE
摘要 PROBLEM TO BE SOLVED: To read/write a signal on a back wire board at low speed by sequentially reading the signals from respective interface boards on a bus line with a common interface following a prescribed rule. SOLUTION: A bus line 16 of a five-bit width, which connects respective slots 12 and a multiplex separation part 15 is formed on a back wire board 11. Respective interface boards 14 interface main signals in a 1.5 M basic path frame units on the back wire board 11, despite of the interface speed of main signals which the boards store. In such a case the main signals from the interface boards 14 at speed exceeding 1.5 Mbps are divided into a plurality of 1.5 M basic path frames. Namely, the signal of 6.3 Mbps interface is stored by using four 1.5 M basic path frames. The signal of 8 Mbps interface is stored by using five frames and the signal of 50 Mbps by using 28 frames.
申请公布号 JP2000049743(A) 申请公布日期 2000.02.18
申请号 JP19980215371 申请日期 1998.07.30
申请人 TOYO COMMUN EQUIP CO LTD 发明人 AOKI HIROO;ITO TSUKASA;MATSUI TOSHIAKI;SAITO TOSHIAKI;KONDO MASAMI
分类号 H04J3/04;H04J3/22;(IPC1-7):H04J3/22 主分类号 H04J3/04
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