| 摘要 |
PROBLEM TO BE SOLVED: To provide a product-sum operating unit and an image processor which can be constituted at a low cost, and to increase the number of processible data. SOLUTION: Image data stored in a frame buffer 128 are area in a prescribed sequence by a CPU 129, and successively outputted to a latch circuit 110 as input signals Si. An SRAM 113 successively stores the image data outputted from a latch circuit 108, and outputs the stored image data to a latch circuit 103. Image data latched by latch circuits 101-109 are multiplied by multiplier data latched by a latch circuit 116 by multiplying circuits 117-125, and added by an adding circuit 126, and divided by a dividing circuit 127. Thus, a smoothing processed image data output signal S0 is outputted.
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