发明名称 TESTER FOR SEMICONDUCTOR CMOS INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress increase of chip area by controlling even a semiconductor CMOS integrated circuit having a DC path previously by means of a test circuit for IDDQ thereby performing IDDQ test without interrupting the DC path. SOLUTION: Net stationary current consumption of a DUT(device under test) 102 and a current containing a leakage current in failure or insufficient breakdown voltage are determined by adding the all input currents of a first high accuracy current measuring unit 101 for measuring the stationary power supply current and converting it to a voltage and second high accuracy current measuring units 103a1-103aN for measuring each input current of the DUT 102 and converting it to a voltage and then subtracting the total input current with a subtractor 105 from the stationary power supply current containing the through current of a DC path. A comparison/decision circuit 106 compares the stationary power supply current of the DUT 102 thus operated with a preset decision reference level thus making a decision whether the DUT 102 is acceptable or not.
申请公布号 JP2000046896(A) 申请公布日期 2000.02.18
申请号 JP19980213575 申请日期 1998.07.29
申请人 SHARP CORP 发明人 KAMATA TORU
分类号 G01R31/26;H01L21/822;H01L27/04;(IPC1-7):G01R31/26 主分类号 G01R31/26
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