| 摘要 |
PROBLEM TO BE SOLVED: To reduce the deviation between the optimum timing of an equalizer and the sampling timing of an AD converter without increasing the arithmetic quantity of the equalizer. SOLUTION: A changeover switch 125 is controlled and switched with a control signal c2, an error signal outputted by a digital computing element 123 at the end of the former half of a training period is stored in a memory 126, and an error signal at the end of the training period is stored in a memory 127. A decision unit 129 decides which of the errors at the end of the former half of the training period and at the end of the training period is larger and controls a changeover switch 130. Consequently, when the error at the end of the former half of the training period is larger, a sampling clock is outputted to an AD converter 101 as it is and when not, the sampling clock is delayed by a 1/2 sampling cycle through a delay unit 131 and outputted to the AD converter 101.
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