CLOCK SYNCHRONIZING MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a clock synchronizing memory for accurately and easily synchronizing data with a clock even in the case of different delay lines between respective memory cells in the memory having a plurality of memory cells like an SLDRAM. SOLUTION: A very small delay regulator 10 has a counter 2, a decoder 4 for decoding the coefficient output of the counter 2 to output a predetermined selection signal according to the decoded result, and a delay unit 6 inputting the output of the counter 2 and the output of the decoder 4 to delay a clock at a part for inputting the selection signal.