| 摘要 |
PROBLEM TO BE SOLVED: To provide a static semiconductor memory in which no standby current fault occurs even by short-circuiting a bit line and a line of a ground potential. SOLUTION: A bit line load controller 13 of an SRAM generates control signalsϕA,ϕB in response to internal read/write signal int/WE, internal chip selection signal int/CS and a word line activation signal WLE. At the time of a standby mode, signalsϕA,ϕB respectively become an 'L' level and an 'H' level, and both MOS transistors of a bit line load circuit become non- conductive. Thus, leakage current to a fault bit line grounded from a line of a power source voltage VCC is curtailed.
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