发明名称 OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To attain a low cost by the reduction of the number of elements, to secure the stability of an output action even when the fluctuation exists in manufacture process and, besides, to facilitate through rate adjustment in a through-rate control type output buffer circuit. SOLUTION: A pMOS transistor 10 is driven not by an arithmetic amplifier but by an nMOS transistor 22, the nMOS transistor 11 is driven not by an arithmetic amplifier but by the pMOS transistor 23 and, besides, a bias circuit 21 is constituted of the pMOS transistors 15 and 24 and the nMOS transistor 16 and 25 without using a fixed resistance.
申请公布号 JP2000049585(A) 申请公布日期 2000.02.18
申请号 JP19980216582 申请日期 1998.07.31
申请人 FUJITSU LTD 发明人 OGUSHI NORIAKI
分类号 H01L27/04;G06F13/00;H01L21/82;H01L21/822;H03K19/003;H03K19/0175;H03K19/0185;H03K19/094;(IPC1-7):H03K19/017 主分类号 H01L27/04
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