| 摘要 |
PROBLEM TO BE SOLVED: To realize a rewritable logical circuit without using a tri-state buffer. SOLUTION: Plural cells 1 are connected in a network state by input signal lines Pwi, Pni, Pei and Psi and output signal lines Pwo, Pno, Peo and Pso, the respective cells 1 are provided with rewritable logical memories Mw, Mn, Me and Ms and the logical memories Mw, Mn, Me and Ms read previously stored values by a common address value which is inputted through the input signal lines Pwi, Pni, Pei and Psi and outputs them to the corresponding output signal lines Pwo, Pno, Peo and Pso.
|
