发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To monitor an inner voltage including a boosted voltage and a negative voltage through a simple arrangement by dividing the differential potential between a boosted voltage and a second voltage or between a first voltage and a negative voltage between first and second potentials and outputting it through an MOSFET which is turned on under a predetermined mode. SOLUTION: An inner voltage generating circuit comprises a booster circuit, a voltage drop circuit and a negative voltage generating circuit. A dividing voltage is determined by the ratio of size between MOSFETs: Q1, Q2. At the time of test operation for monitoring VBB, a test signalϕTT has high level andϕTB has low level. The high levelϕTT employs a power supply voltage VDD when the differential voltage between the power supply voltage VDD and the dividing voltage is higher than the threshold level Vth of an MOSFET: Q4 otherwise employs a boosted voltage. Consequently, a dividing voltage (VDD-VBB)/2 is outputted, as it is, from an external terminal Ai regardless of the threshold level Vth of an MOSFET: Q4.
申请公布号 JP2000048600(A) 申请公布日期 2000.02.18
申请号 JP19980216366 申请日期 1998.07.31
申请人 HITACHI LTD;HITACHI ULSI SYSTEMS CO LTD 发明人 MURANAKA MASAYA;ITO YUTAKA;OYAMADA MASAHIRO;TAKAHASHI AKIRA
分类号 G11C11/413;G11C11/401;G11C11/407;G11C11/409;G11C29/00;G11C29/12;H01L21/822;H01L27/04;(IPC1-7):G11C29/00 主分类号 G11C11/413
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