| 摘要 |
PROBLEM TO BE SOLVED: To enhance the reliability in a PLL(phase locked loop) circuit and in a logical integrated circuit device including it by realizing the PLL circuit by which a lock-in state can be recovered after automatically escaping from a runaway state. SOLUTION: A phase comparing circuit PD for comparing the phase of an input clock signal Pin with that of a feedback clock signal Pfb, a charge pump circuit CP for generating a control voltage VC in accordance with an up signal Up and a down signal DN which are outputted from the phase comparing circuit PD, a voltage control type oscillation circuit VCO for generating an output clock signal Pout in accordance with the control voltage VC and a frequency dividing circuit FD for dividing the frequency of the output clock signal Pout and generating the feedback clock signal Pfb are included in this PLL circuit. The PLL circuit is provided with an abnormality detecting circuit TD for judging that the output clock signal Pout escapes from a lock-in possible area and an abnormality recovering circuit TC for receiving these output signals CC0-CC2 and resetting the potential of the control voltage VC to a prescribed value. A judgement time by the abnormality detecting circuit TD is optionally set. |
