| 摘要 |
PROBLEM TO BE SOLVED: To provide a DLL(delay locked loop) circuit which is normally operated even when a supply clock becomes a low frequency. SOLUTION: This DLL circuit for delaying a reference clock and generating a control clock having prescribed phase relation is provided with a variable delay circuit 14 where the reference clock N2 is inputted and a clock N3 is outputted, a phase comparator 16 comparing it with a delay clock N5 and a delay control circuit 15 generated a delay control signal ϕE so that the phases of the clocks N2 and N5 become in prescribed relation. Moreover, the DLL circuit is provided with a definite multiplication clock generator generating a definite multiplication clock N11 and a selecting circuit 32 selecting either of a supply clock N10 or the definite multiplication clock N11 and outputting it as the reference clock. Since the definite multiplication clock generator 31 is disposed, an external clock is utilized as the reference clock by making it high speed even when the speed is low (low frequency). |
