| 摘要 |
PROBLEM TO BE SOLVED: To prevent the degradation of wiring reliability attributable to stress in a region between the upper layer side plug and the lower layer side plug in a multilayer wiring structure of a semiconductor device, having a stack structure. SOLUTION: In a multilayer wiring structure where a resistance variation occurs after being maintained at a high temperature for a long time, a void 40 was observed in a wiring 4 interposed between the upper layer side plug 3 and the lower layer side plug 6. Portion 43, 44 interposed between the upper layer side plug 3, and the lower layer side plug 6 have smaller crystal grains in size than those in other regions and a planar orientation different from other regions. Therefore, to increase the wiring reliability, the contact surface of the upper layer side plug, and the wiring and that of the lower layer surface side plug and the wiring are off-centered to reduce stress imposed on the wiring. When the aluminum or aluminum alloy layer of the wiring is formed, the sputtering temperature is set so that the region sandwiched between the upper layer side plug and the lower layer side plug does not have crystal grain boundaries.
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