发明名称 METHOD AND EQUIPMENT FOR MEASURING OVERLAP LENGTH OF MISFET, RECORDING MEDIUM WITH EXTRACTION PROGRAM AND DEVICE MODEL RECORDED THEREIN
摘要 PROBLEM TO BE SOLVED: To determine one of physically important device parameters, i.e., overlap lengthΔL, accurately at the time of circuit simulation of an MOSFET. SOLUTION: This equipment for measuring a gate-substrate capacitance CGB, excluding fringe capacitance and overlap capacitance for each gate voltage and deriving an overlap lengthΔL based on the measurements, comprises a unit 2 performing electric measurement required for calculating the gate- substrate capacitance CGB for a group of elements, an input unit 3, e.g. a keyboard, a medium 4 recording processing programs (electric measurement control program 4a, capacitance calculating program 4b, regression line deriving program 4c, gate length calculating program 4d, and overlap length extracting program 4e), a data processor 5 which operates under control of the processing programs, a memory 6 for temporarily storing measurement data and operation data, and an output unit 7.
申请公布号 JP2000049339(A) 申请公布日期 2000.02.18
申请号 JP19980213335 申请日期 1998.07.28
申请人 NEC CORP 发明人 TAMEGAYA YUKIO
分类号 G06F17/50;H01L21/66;H01L29/78;(IPC1-7):H01L29/78 主分类号 G06F17/50
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