| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of transistors for constituting a NAND circuit by decreasing the number of input wirings of a decoder and the number of reset timing signal wirings of the decoder in a DRAM. SOLUTION: A decoder has a series connection of two or more transistors, and an N-channel transistor Q8. The series connection is obtained by connecting two or more another N-channel transistors Q1, Q2 in series and further connecting one P-channel transistor Q7 in series. A power source voltage VS is applied to an electrode of one end of the series connection, a bit line precharge signal is input to the electrode of the other end, and predecode signals are respectively input to gates of the two or more transistors Q1, Q2. Then, a bit line precharge signal is input to a gate of the transistor Q8, a drain is connected to a gate of the transistor Q7, and a source is grounded.
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