Circuit for detecting loss of periodic logic signal in phase locked loops or clock signal circuits, uses a divide-by-two divider

摘要

Signal (IN) loss detection circuit (10) includes a divide-by-two frequency divider (12), which receives the input signal, and has two complementary outputs combined with a reference signal (REF) of the same frequency as the input signal, via two similar logic AND gates. Output of a first (14) logic gate is connected so as to increment a first counter (16) and to zero reset a second counter (18) similar to the first. Output of the second logic gate (20) is connected so as to increment the second counter (18) and to zero reset the first counter (16). An OR logic gate (22) produces a loss detection signal when any one of the two counters reaches a pre-determined value . The counters are shift registers including three flip-flops (D1,D2,D3) connected in series. The OR gate is connected to the output of the third flip-flop of each of the two counter (16,18).