Integrated memory device with inter-array redundancy

摘要

Integrated storage device includes storage or memory arrays (B) which comprise memory cells (MC) each arranged at the crossing points of column (BL) and row (WL) lines, at least one redundant row line (RWL) for replacing each one of the row lines in any of the memory arrays as well as a deactivation unit (AKT) for deactivating the memory array. Each of the deactivation lines (EN1--K) is connected to one input of the deactivation unit (AKT) of one of the memory arrays (B). The memory arrays (B) each have a deactivation decoder (ENDEC) connected on the output side to the deactivation lines (EN1--K) associated with the other memory arrays (B). In the event of replacement of one of the row lines (WL), the deactivation decoder (ENDEC) is deactivated via the corresp. deactivation line (EN1--K).