A DELAY LOCKED LOOP WITH HARMONIC LOCK DETECTION

摘要

A delay locked loop comprising a chain (CHN) of at least two delay elements (DL1 - DLN), of which a first delay element (DL1) has an input for receiving a reference signal (phi0), and of which a last delay element (DLN) has an output for delivering an output signal (phiN); a phase comparator (PHCMP) having a first input (PH1) for receiving the reference signal (phi0), a second input (PH2) for receiving the output signal (phiN), and an output for delivering a binary control signal (Bcntrl); and a converter (CNV) for converting the binary control signal (Bcntrl) into an analog control signal (Acntrl) for controlling a delay time of at least one (DL1 - DLN) of said delay elements (DL1 - DLN). The phase comparator (PHCMP) comprises at least one additional input (Aip) for receiving an output signal (phi1 - phiN-1) of at least one of the delay elements (DL1 - DLN-1) preceding the last delay element (DLN). The state of the binary control (Bcntrl) signal supplied by the phase comparator (PHCMP) is not solely determined by the reference signal (phi0) and the output signal of the phase comparator (PHCMP), but also by the state of one or more output signals of the delay elements not being the first (DL1) or the last (DLN) delay element. Thus, the occurrences of subsequent active edges of the output signals of the delay elements (DL1 - DLN) are registered. These occurrences are in fact the additional information needed by the delay locked loop in order to determine the appropriate binary control signal (Bcntrl) from which the analog control signal (Acntrl) for controlling the delay time of the delay elements (DL1 - DLN) is derived.