| 摘要 |
A convolutional coder (10) for generating a convolutional code (14) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The convolutional coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a data bit. First (20) and second (22) tap registers each store a tap position indicator indicative of tap positions in the shift register that are subject to a logical operation. an input (17) shifts input data into the convolutional coder (10). A logic network (11), coupled to receive the input data and arranged to provide the logical operation, has first (g0) and second (g1) outputs for providing, respectively, first and second output data bits that form the convolutional code (14); The first output data bit is generated in response to the input data and the logical combination of each data bit stored in each storage element identified by the first tap position indicator and the second output data bit is generated in response to the input data and the logical combination of each data bit stored in each storage element identified by the second tap position indicator. <IMAGE> |
