发明名称 CIRCUIT WITH INTERCONNECT TEST UNIT AND A METHOD OF TESTING INTERCONNECTS BETWEEN A FIRST AND A SECOND ELECTRONIC CIRCUIT
摘要 An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
申请公布号 EP0979418(A2) 申请公布日期 2000.02.16
申请号 EP19990901802 申请日期 1999.01.29
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V. 发明人 DE JONG, FRANCISCUS G., M.;MURIS, MATHIAS N., M.;RAAYMAKERS, ROBERTUS M., W.;LOUSBERG, GUILLAUME E., A.
分类号 G01R31/28;G01R31/3185;G06F11/22;G11C29/32 主分类号 G01R31/28
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