发明名称 SCANNING CONVERSION CIRCUIT WITH INTERPOLATING FUNCTION
摘要 PROBLEM TO BE SOLVED: To reduce the scale of a circuit by providing the circuit with plural frame buffers for dividedly storing video data of a certain scanning method and for reading out the video data at timing based on another scanning method and executing the vertical inter-polating processing based on the video data read out from respective frame buffers. SOLUTION: A write control means 1 writes video data 10 in respective frame buffers 2A to 2C at the scanning timing of a personal computer(PC) video signal in each horizontal line. In the mean time, a read control means 3 reads out respective video data 21 to 23 at the scanning timing of an NTSC signal or a PAL signal from respective frame buffers 2A to 2C. In this case, the video data 21 to 23 of three successive lines in the vertical direction are simultaneously read out and inputted to an interpolation means 4. The means 4 generates converted video data 30 from these video data 21 to 23 by prescribed operation processing.
申请公布号 JP2000041224(A) 申请公布日期 2000.02.08
申请号 JP19980208259 申请日期 1998.07.23
申请人 NEC CORP 发明人 SATO SHINOBU
分类号 G06F3/14;G09G5/00;G09G5/18;G09G5/39;G09G5/391;G09G5/395;G09G5/397;G09G5/399;H04N7/01 主分类号 G06F3/14
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