发明名称 METHOD AND DEVICE FOR CONTROLLING CACHE MEMORY
摘要 PROBLEM TO BE SOLVED: To improve a cache hit rate by deciding to be replaced with which cache data based on the count result of the number of cache mishits at the time of a cache mishit. SOLUTION: An address comparator 105 compares the address of data stored in an address storing part 103 with an address transmitted from an instruction issuing part 104 and performs hit/mishit decision. A miscounter part 106-1 counts the number of times when mishit takes place in the comparator 105 and stores the number of misses in every cache line in a mistake storing part 106-2. The parts 106-1 and 106-2 are provided in these ways and are used to decide which block to be rewritten when a cache miss takes place in a load instruction. That is, when a cache mishit occurs, the number of cache mishit of each way is compared, the cache line data of a way that has many mishit are rewritten.
申请公布号 JP2000040030(A) 申请公布日期 2000.02.08
申请号 JP19980209143 申请日期 1998.07.24
申请人 NEC CORP 发明人 FUKAGAWA MASAO
分类号 G06F12/12;G06F12/08;(IPC1-7):G06F12/12 主分类号 G06F12/12
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