| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL(phase-locked loop) circuit which operates at high speed and eliminates the need for adjusting the phase of the clock. SOLUTION: A discriminator 1 discriminates and regenerates input data by a clock signal outputted from a voltage-controlled oscillator 4 and a phase comparator 12 compares the phase of the input data and the phase of a clock signal with each other and outputs a signal '1' of a level representing the advance of the phase by the output signal of the discriminator 1, when the phase of the clock signal advances for the phase of an input signal. When the phase of the clock signal is delayed with respect to the phase of the input signal on the contrary, the phase comparator 2 outputs a signal '0' of a level representing the phase delay to a filter 3 by the output signal of the discriminator, the filter 3 outputs the output signal of the phase comparator 2 to the voltage-controlled oscillator 4 after band adjustment, and the voltage-controlled oscillator varies the frequency of the clock signal according to the voltage of the output signal of the filter 3. |
