发明名称 DEVICE AND METHOD FOR TESTING FLASH MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To shorten the test time without destroying the chip of a flash memory by detecting a minimum voltage executing erasure of the data and applying the voltage lower than the minimum voltage to the source of the flash memory when the burn-in of the flash memory is to be executed. SOLUTION: A Vpp voltage lower than a regular erase voltage is applied to the source 28 of a memory transistor. A CPU 2 reads out the data, and decides whether or not the data are erased, and when the CPU 2 detects the memory transistor where the data are erased, its Vpp voltage is made to the minimum voltage. When the voltage lower than the minimum voltage by 1V range is applied to the source 28 of the memory transistor, the CPU 2 reads out the data to decide whether or not the memory transistor where the data are erased exists. When the CPU 2 detects the memory transistor that the data are erased, the memory transistor is determined as a defective chip.</p>
申请公布号 JP2000040399(A) 申请公布日期 2000.02.08
申请号 JP19980203764 申请日期 1998.07.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUENAGA KOICHI
分类号 G01R31/28;G11C16/06;G11C29/00;G11C29/06;(IPC1-7):G11C29/00 主分类号 G01R31/28
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