发明名称 CMOS MULTIPLICATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a highly practical CMOS multiplication circuit capable of being formed on a semiconductor integrated circuit and being normally operated. SOLUTION: So as to make four transistor pairs (M1 and M5, M2 and M7, M3 and M6, M4 and M8) for which N channel transistors and P channel transistors whose sources are connected in common are serially connected be all different, the gates (M1 and M2, M3 and M4) of the two N channel transistors with each other and the gates (M5 and M6, M7 and M8) of the P channel transistors with each other are connected in common and the input terminal pairs of a multiplier core circuit are respectively constituted. In this case, one input terminal pair is constant current driven and signals are inputted through an input circuit for which the N channel transistors (M10 and M12) and the P channel transistors (M9 and M11) whose sources are connected in common are serially connected.
申请公布号 JP2000040118(A) 申请公布日期 2000.02.08
申请号 JP19980209146 申请日期 1998.07.24
申请人 NEC CORP 发明人 KIMURA KATSUHARU
分类号 G06G7/163;H03F3/45;H03K19/0948;(IPC1-7):G06G7/163;H03K19/094 主分类号 G06G7/163
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