| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of reducing power consumption at the time RAS(row address strobe signal) is in an 'L' stand-by by controlling operations of buffer circuits for internal step-down voltage. SOLUTION: This memory is a 64M-bit DRAM and it is constituted of a memory array and its peripheral circuits or the like and in the internal step- down power source circuit to be incorporated in the internal power source voltage generating circuit of the peripheral circuit. An internal power source voltage down level sensor VDLS and plural internal step-down level buffer circuit VDLB are included. The internal step-down source circuit is constituted so as to prohibit operations of buffer circuits for internal step-down power source VDLB1 of one part of the circuit by controlling operations of other internal step-down level buffer circuit VDLB1 except a minimum internal step- down level buffer circuit assuring the 'L' stand-by state of the RAS among the buffer circuits for internal step-down power source VDLB by the output of the sensor VDLS while operating the internal power source voltage level sensor VDLS at the time the RAS is in the 'L' stand-by.
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