发明名称 |
Integrated circuit device having a memory array with segmented bit lines and method of operation |
摘要 |
An integrated circuit device having a memory array (50) with segmented bit lines and a method of operation are disclosed. A sub array (52) of the memory array (50) can be operated as a multiple port sub array. A bit line of the sub array (52) is separated into bit line segments by disconnecting the bit line segments (54) from one another. A first bank of sense amplifiers (58) is connected to a first bit line segment (54) of the sub array (52), and a second bank of sense amplifiers (58) is connected to a second bit line segment (54) of the sub array (52). A first operation is performed to the first bit line segment (54) using the first bank of sense amplifiers (58), and a second operation is concurrently performed to the second bit line segment (54) using the second bank of sense amplifiers (58).
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申请公布号 |
US6023428(A) |
申请公布日期 |
2000.02.08 |
申请号 |
US19980123591 |
申请日期 |
1998.07.28 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
TRAN, HIEP VAN |
分类号 |
G11C7/10;G11C7/18;G11C11/4097;(IPC1-7):G11C16/04 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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