发明名称 |
D FLIP-FLOP |
摘要 |
PURPOSE: A D flip-flop is provided to reduce an entire layout area by decreasing the number of gates. CONSTITUTION: The D flip flop comprises: a master terminal latching an outer input; a slab terminal input and latching the latched data to the master terminal; the first transmitting circuit receiving the outer data by responding the first and the second clock signal of a complementary level; a first latch circuit(10) preserving the latched data to the master terminal by responding the clock signal; and a second latch circuit(20) preserving the outer input data by connecting between the first transmitting circuit and the latch circuit.
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申请公布号 |
KR20000007307(A) |
申请公布日期 |
2000.02.07 |
申请号 |
KR19980026586 |
申请日期 |
1998.07.02 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
MOON, JAE YOUNG |
分类号 |
H03K5/00;(IPC1-7):H03K5/00 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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