SEMICONDUCTOR MEMORY DEVICE AND DATA READ METHOD

摘要

PURPOSE: A semiconductor memory device is provided to perform a two cycle pipeline operation without an error in response to a high and a low frequency. CONSTITUTION: The semiconductor memory device comprises: a sense amplifier unit(20) for amplifying data read from a memory cell array in response to a sense amplification enable signal to generate a sense output signal pair; and a data output buffer(22) for buffering and outputting the sense output signal pair, wherein the data output buffer comprises a level shifter(60) for generating a first data output signal pair, a register(62) for generating a second data output signal pair, a first transfer and latch part(64) for transferring the second data output signal pair to generate a third data output signal pair, a second transfer and latch part(66) for transferring the data output signal pair to generate a fourth data output signal pair, a first inversion part(72) for inverting the third data output signal pair to generate a fifth data output signal pair, a second inversion part(74) for inverting the fourth data output signal pair to generate the fifth data output signal pair, and a logic multiplication part(78) for logically multiplying fifth data output signals of the pair in response to a data output enable signal.