ABSOLUTE ENCODER

摘要

An absolute encoder which can generate an absolute value signal with a simple operation processing. The encoder generates an absolute value signal A01=f having the number of pitches (a0-a1) and obtained by expressing phase signals phi 0 to phi 3 respectively by j-bit digital signals, subtracting a signal b obtained by dividing the phase signal phi 0 by 2<K1> (K1, an integer) from a phase difference signal phi 01=C, and using the high-order K1-bit signal of the subtracting signal as high-order bits and phi 0 as low-order bits; generates an absolute value signal A02=k having the number of pitches (a0-a2) and obtained by subtracting a signal g obtained by dividing A01=f by 2<K2> (K2, an integer) from a phase difference signal phi 02=h, and using the high-order K2-bit signal of the subtracting signal as high-order bits and f as low-order bits; generates a longer-pitch absolute value signal by performing the above sequences; gradually processes signals in the order of increasing pitch length to eliminate a condition in which a pitch number cannot be specified; permits a larger allowance value of a phase error between slits; and can correct and adjust by PLL a phase difference signal error at a high-speed rotation of a scale.