发明名称 LOW SWITCHING NOISE LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress noise generated at a resistance or impedance of a power line by setting a time constant formed of an added capacity element and a resistance element to sufficiently larger specific constant formed of a load capacity and an ON resistance or the like of a transistor of a CMOS logic circuit. SOLUTION: An inverter is constituted between a power source Vdd and a ground GND1. Attached capacitors C1, C2 having sufficiently larger capacities than a load capacity are selected. In the case of outputting at a Hi level, positive charge is supplied not from the power source Vdd but the capacitor C1 to the load capacity CL, and the capacitor C1 is rapidly charged with lost charge from the power source at a larger time constant. In the case of outputting at a Low level, the charge stored in the capacitor CL is once transferred to the capacitor C2, and the charge stored in the capacitor C2 is discharged slowly to the ground GND at a large time constant. Thus, a transient current is reduced to reduce a switching noise.
申请公布号 JP2000036561(A) 申请公布日期 2000.02.02
申请号 JP19980203523 申请日期 1998.07.17
申请人 HANDOTAI RIKOUGAKU KENKYU CENTER:KK 发明人 IWATA ATSUSHI;NAGATA MAKOTO;HIJIKATA KATSUMASA
分类号 H01L27/04;H01L21/822;H03K19/003;H03K19/0948;(IPC1-7):H01L27/04 主分类号 H01L27/04
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