| 摘要 |
PROBLEM TO BE SOLVED: To provide the control method of a bus capable of improving bus using efficiency by reducing the overheads of data transfer. SOLUTION: A module (master) 100 for performing read access to the module 101 to be a slave requests a bus using right to a bus arbiter by BREQ signals 61 and reports that the next cycle is the last cycle to be used by the master by LC signals 63. Then, when bus use is permitted by BGRANT signals 62, the read access is activated by transferring an address to the slave 101 by using the A/D 50 of a system bus in the next cycle and the bus using right is released. Only in the case of being incapable of receiving the transferred address, the slave 101 asserts RETRY signals 55 two cycles after the transfer cycle of the non-received address. The module 100 which executes transfer two cycles before the cycle in which the RETRY signals 55 are asserted executes the transfer executed two cycles before again.
|
