发明名称 BUS CONTROLLING METHOD
摘要 PROBLEM TO BE SOLVED: To reduce bus occupying time and to improve bus use efficiency by always performing transfer in one cycle per data or address after acquiring the right of use of a bus. SOLUTION: A master 100 which acquires the right of use of a bus communicates data to at least one slave 101, etc., which synchronizes with a clock signal that is common to all modules 100 to 107. The master module 100 continuously executes plural transmission cycles in which data is communicated to the slave 101, etc., after acquiring the right of use of a bus and releases the right of use of a bus after executing the first one cycle of the transfer cycles. And, it conforms if a retry request is issued from at least one of the slave 101, etc., in a preliminarily defined cycle after releasing the right of use of a bus and when the retry request is not received, the next transfer cycle is carried out. It is preferable that a preliminarily defined cycle here is two cycles after releasing the right of use of a bus.
申请公布号 JP2000035944(A) 申请公布日期 2000.02.02
申请号 JP19990136463 申请日期 1999.05.17
申请人 HITACHI LTD 发明人 KONDO NOBUKAZU;KANEKO SEIJI;GENMA HIDEAKI;OKADA TETSUHIKO;KOMORI KAZUHIKO;OKAZAWA KOICHI
分类号 G06F13/362;G06F13/42;(IPC1-7):G06F13/362 主分类号 G06F13/362
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