发明名称 ERROR CORRECTION CIRCUIT AND ERROR CORRECTING METHOD
摘要 PROBLEM TO BE SOLVED: To provide an error correction circuit and an error correcting method to decode data with no generation of cosets by means of a trellis decoder that has (n) types of states, i.e., can perform the decoding operations in plural different types of states. SOLUTION: A branchmetric generation circuit 201 generates the branchmetrics against each of code data. An ACS circuit 202 adds together the branch metrics and path metrics of every state and compares these sums with each other to select the least sum as a new path metric of every state. The data corresponding to a selected path of each state are stored in a path memory. A trace-back processing circuit 204 traces a survivor path, having the least new path metric back to a point of time that is decided by the discontinued path length and decodes the data Y2Y1 (4-states) or data X2X1 (8-state). In such a constitution, the data can be decoded by a trellis decoder which is used in common to 4 and 8 states respectively.
申请公布号 JP2000036764(A) 申请公布日期 2000.02.02
申请号 JP19990133360 申请日期 1999.05.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KISODA AKIRA;SENDA HIROYUKI;KAMATA TAKEHIRO
分类号 H04L27/04;H03M13/23;H03M13/25;H03M13/41;(IPC1-7):H03M13/23 主分类号 H04L27/04
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