发明名称 CIRCUIT AND METHOD OF MODULO MULTIPLICATION
摘要 A co-processor (44) executes an arithmetical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in a summer (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value.
申请公布号 WO0005645(A1) 申请公布日期 2000.02.03
申请号 WO1999US00826 申请日期 1999.01.13
申请人 MOTOROLA INC. 发明人 FOSTER, ROBERT, I.;BUSS, JOHN, MICHAEL;TESCH, RODNEY, C.;DWORKIN, JAMES, DOUGLAS;TORLA, MICHAEL, J.
分类号 G06F7/00;G06F7/72;G06F17/10;G09C1/00;(IPC1-7):G06F7/72 主分类号 G06F7/00
代理机构 代理人
主权项
地址