| 摘要 |
PROBLEM TO BE SOLVED: To end a sleep state in the proper timing and in consideration of both frequency and phase errors between the slow and fast clocks. SOLUTION: A 1st clock circuit 20, which supplies a slow clock, a 2nd clock circuit 30 which supplies a fast clock, a power control part 10 which supplies power to operate the circuit 30, a receiving part 60 whose receiving operation is controlled by the clock to be supplied, a switch 50, a control part 40 which controls the intermittent actions of the part 60, a frequency error detection part 41 which detects frequency errors between the slow and fast clocks, a phase error detection part 42 which detects phase errors between the slow and fast clocks, and a wait timing calculation part 43 which decides the timing to switch the part 60 from a sleep state to a wake state in the timing, where both frequency and phase errors caused between the slow and fast clocks are reflected are provided.
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