发明名称 CORRELATOR AND DELAY LOCK LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the circuit scale and to shorten a code phase detection time that is needed for initial synchronization. SOLUTION: A combined code generation part 22 of a correlator weights plural reference spread codes A1 to AM, having phases which are shifted with respect to each other and combines them to output a combined spread code with respect to a spread spectrum signal. An arithmetic circuit 23, at the same time calculates correlations between a receiving spread code and the codes A1 to AM. Then a phase detection circuit 24 detects the phase difference between the receiving spread code and the reference spread code, i.e., the phase of the receiving spread code.
申请公布号 JP2000036775(A) 申请公布日期 2000.02.02
申请号 JP19980203237 申请日期 1998.07.17
申请人 FUJITSU LTD 发明人 OISHI YASUYUKI;HASE KAZUO;HAMADA HAJIME;ASANO MASAHIKO
分类号 H04B1/707;H04B1/7075;H04B1/7085;H04B1/709;H04B1/7095;H04L7/00 主分类号 H04B1/707
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