发明名称 VOLTAGE GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To attain low power consumption so as to be capable of operation on a P-type substrate, by eliminating the need for using a pulse train as an input signal. SOLUTION: This voltage generating circuit consists of a capacitance transistor C1, a delay element DL1 which is connected between an input terminal TIN and an input terminal of C1 and delays an input signal IND, a P-channel type transistor P1 whose source is connected to a power source VDD, whose drain is connected to an output terminal of C1 respectively, and which receives supply of a reversing signal of the input signal IND into a gate, and a transistor P2 of P-channel type whose source is connected to the output terminal of C1, whose drain is connected to a ground GND respectively, and which receives supply of the input signal IND in the gate. An electric charge of C1 is discharged in response to a transition from H level to L level of the input signal IND, and a negative voltage of -VDD is generated in response to a transition to L level of a potential of the input terminal of C1 after a lapse of delay time.
申请公布号 JP2000037071(A) 申请公布日期 2000.02.02
申请号 JP19980200177 申请日期 1998.07.15
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 KISHIYAMA EIJI
分类号 G11C11/413;G11C11/407;H02M3/07;(IPC1-7):H02M3/07 主分类号 G11C11/413
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