| 摘要 |
<p>An improved design and method of a digital decimation and interpolation filter for a multi-bit input signal, reduces the buffer requirement during a decimation operation and relieves the processing bottleneck during an interpolation operation through the use of transposition of an FIR filter structure having time-varying coefficients. The design includes an input lead (120), a multiplier (122), a accumulator (132), a memory (128), a shift register (132), an output buffer (138) and a sequencer (140). The input lead receives the digital input signal. The multiplier (122) having a first and second multiplier input terminal coupled to the input lead (120) at its second multiplier terminal receives the digital input signal. The memory (128), having stored coefficient sets, is coupled to the first multiplier input terminal. The sequencer (140), coupled to the memory (128) and the output buffer (138), transfers each coefficient set to the first multiplier input terminal. The accumulator (132), coupled to the multiplier (122), determines partial sums of the output sample y(n) by summing the products supplied by multiplier (122) . The accumulated product is stored in the shift register (136) and; thereafter, transferred to the buffer memory (138). The buffer memory (138), coupled to the accumulator, receives and stores the accumulated output sample y(n). <IMAGE></p> |
