| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce distortion stress under thermal shock environment, and to improve electric connection reliability, by making specific a coefficient of thermal expansion in the surfaces of a carrier wiring board and a mother wiring board, and at the same time by setting the coefficient of thermal expansion on the surface of the carrier wiring board larger than that of the mother wiring board. SOLUTION: With a carrier wiring board 6 and a mother wiring board 1, an electrode 11 being provided on the rear surface of the carrier wiring board 6 is electrically connected to an electrode 12 being provided on the upper surface of the mother wiring board 1 via a connection conductor 13 such as a soldering ball. Then, a coefficient of thermal expansion CTE on the surfaces of the carrier wiring board 6 and the mother wiring board 1 is set to 10-16 ppm/ deg.C, and at the same time the CTE on the surface of the carrier wiring board 6 is set larger than that of the mother wiring board 1, thus maintaining the proximity relationship between an electronic component 7 with a low CTE such as a semiconductor element and the CTE of the carrier wiring board 6 where the electronic component 7 is directly mounted, and hence improving electric connection reliability.</p> |
