Signal processor with independently arithmetic and logic unit and multiplier accumulator unit simultaneously operable,申请号EP19900480126-传众专利搜索

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发明名称	Signal processor with independently arithmetic and logic unit and multiplier accumulator unit simultaneously operable
摘要
申请公布号	EP0425410(B1)	申请公布日期	2000.02.02
申请号	EP19900480126	申请日期	1990.08.29
申请人	INTERNATIONAL BUSINESS MACHINES	发明人	JONES, GARDNER DULANY, JR.
分类号	H03H17/02;G06F7/57;G06F9/38;G06F15/78;G06F17/10;G06F17/14;(IPC1-7):G06F9/38	主分类号	H03H17/02
代理机构		代理人
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