发明名称 REWRITABLE LOGIC CIRCUIT AND LATCHING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a rewritable logic circuit which uses not a transfer gate switch, but a reconstitutable wiring logic element. SOLUTION: Cells 1 are connected through signal paths Pw, Pn, Pe, and Ps, and have rewritable logic memories Mw, Mn, Me, and Ms having a tristate output function, set the signal paths for input or output, when the tristate output function is set, and read previously stored values out of the logic memory by accessing the memory by using as addresses values inputted through the signal path set for input, thereby outputting them to the signal path set for output.
申请公布号 JP2000036738(A) 申请公布日期 2000.02.02
申请号 JP19980239794 申请日期 1998.08.26
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 OGURI KIYOSHI;ITO HIDEYUKI;KONISHI RYUSUKE;ISHII KENJI
分类号 G06F7/501;G06F7/50;H03K3/037;H03K19/177;(IPC1-7):H03K19/177 主分类号 G06F7/501
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