发明名称 Field effect transistor array including resistive interconnections
摘要 A semiconductor device includes a high-power output transistor chip in which transistor cells are connected in parallel, each transistor cell including stripe-shaped gate electrodes connected to a gate bus, stripe-shaped drain electrodes connected to a drain pad, and stripe-shaped source electrodes connected to a source pad, wherein the drain electrodes and the source electrodes are alternatingly arranged and pairs of source and drain electrodes face each other across one of the gate electrodes; and a resistor including a portion of the gate bus between adjacent transistor cells, for preventing oscillation between the adjacent transistor cells. Since the resistor serves as a loss component, oscillation due to an imbalance in characteristics between adjacent transistor cells is cancelled so that the synthesis efficiency of the transistor cells is improved. Furthermore, since the resistor is disposed between adjacent cells, this resistor does not act as a loss unless oscillation occurs due to an imbalance in characteristics between the adjacent cells. Thus, there is no possibility that the resistor might increase gate resistance or parasitic capacitance and, therefore, it is possible to stabilize the operation of the transistor by preventing oscillation, without reducing the gain of the transistor.
申请公布号 US6020613(A) 申请公布日期 2000.02.01
申请号 US19980048891 申请日期 1998.03.27
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 UDOMOTO, JUNICHI;KOMARU, MAKIO
分类号 H01L27/04;H01L21/285;H01L21/338;H01L21/822;H01L23/482;H01L23/58;H01L29/423;H01L29/812;(IPC1-7):H01L29/78 主分类号 H01L27/04
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