| 摘要 |
The present invention relates to an address transition detection (ATD) circuit that generates an address transition detection signal having a prescribed pulse width by detecting a logic transition of an input address bit. The ATD circuit includes a low-to-high first delaying circuit that receives the address bit to delay an output of the address bit of high level but outputs the address bit of low level without a delay. A high-to-low second delaying circuit receives the address bit to output the address bit of high level without a delay, but delays an output of the address bit of low level. A logic gate receives address bit from the first and second delaying circuits output to an address transition detection signal. A feed-back control circuit receives the address transition detection signal to cancel a delaying process of the first and second delaying circuits.
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