发明名称 |
Limited latch linehold capability for LBIST testing |
摘要 |
A method of LBIST testing of the entire chip logic whereby intermittent faults can be eliminated. LBIST control logic is programmed to apply linehold states to specified latches within the chip. Latches which feed logic that has intermittent faults can be held to a specified '0' or '1' state such that the intermittent faults causing intermittent signatures can be eliminated. LBIST testing can proceed on looking for the next failure, if one existed, or proving that the remaining logic contains no faults. The LBIST design contains logic for generating linehold controls that will apply a specified linehold state to selected latches during the scan operation portion of the LBIST test.
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申请公布号 |
US6021514(A) |
申请公布日期 |
2000.02.01 |
申请号 |
US19980012047 |
申请日期 |
1998.01.22 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KOPROWSKI, TIMOTHY JOHN |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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