| 摘要 |
A logic controller apparatus for solving ladder logic includes first memory locations for storing representations of the ladder logic and second memory locations for storing a plurality of input and output digital logic signals. A processor employs at least some of the digital logic signals for solving the representations of the ladder logic. A representation of ladder logic power flowing from a power rail to a neutral rail flows in a forward direction from a first port to a second port of at least one of a plurality of ladder functional devices, such as contacts. The contacts are organized in a plurality of rows which include at least one of the contacts. The ladder logic power representation also flows in a reverse direction from the second port to the first port of at least another one of the functional devices.
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