发明名称 |
Composite metallization structures for improved post bonding reliability |
摘要 |
Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads. The portions of the plurality of patterned features are composite metallization regions that have a plurality of deformation preventing oxide patterns that are resistant to compression force induced plastic deformation that occurs when the plurality of gold bonding wires are applied.
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申请公布号 |
US6020647(A) |
申请公布日期 |
2000.02.01 |
申请号 |
US19980215902 |
申请日期 |
1998.12.18 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
SKALA, STEPHEN L.;BOTHRA, SUBHAS;PRAMANIK, DIPU;SHU, WILLIAM KUANG-HUA |
分类号 |
H01L23/485;(IPC1-7):H01L29/41 |
主分类号 |
H01L23/485 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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