Information processing device and control method thereof

摘要

An operation for achieving consistency among copies existing in a plurality of cache memories in a parallel computer system was performed per transaction. If an access issued from a processor to a cache memory is a synchronous access, seeking of a DIRTY block in the cache memory is started. The cache memory issues a bus transaction onto a system bus and performs write back of the DIRTY block in the cache memory relative to a main memory. The write back bus transaction issued from the cache memory in the foregoing fashion is snooped by the other cache memory. With this arrangement, an unnecessary consistency holding operation can be omitted to reduce a delay upon memory accessing in a parallel computer system employing a loose memory consistency model.